A link layer processor is one example of what is more generally referred to herein as a link layer device, where the term “link layer” generally denotes a switching function layer. Such link layer devices can be used to implement processing associated with various packet-based protocols, such as Internet Protocol (IP) and Asynchronous Transfer Mode (ATM).
Communication between a physical layer device and a link layer processor or other type of link layer device may be implemented in accordance with an interface standard, such as the SPI-3 interface standard described in Implementation Agreement OIF-SPI3-1.0, “System Packet Interface Level 3 (SPI-3): OC-48 System Interface for Physical and Link Layer Devices,” Optical Internetworking Forum, 2001, which is incorporated by reference herein.
A given physical layer device may comprise a multiple-port device which communicates over multiple channels with the link layer device. Such communication channels, also commonly known as MPHYs, may be viewed as examples of what are more generally referred to herein as physical layer device ports. A given set of MPHYs that are coupled to a link layer device may comprise multiple ports associated with a single physical layer device, multiple ports each associated with one of a plurality of different physical layer devices, or combinations of such arrangements. As is well known, a link layer device may be advantageously configured to detect backpressure for a particular MPHY via polling of the corresponding MPHY address on its associated physical layer device. The detected backpressure is used by the link layer device to provide flow control and other traffic management functions, thereby improving link utilization.
U.S. Patent Application Publication No. 2005/0005021, published Jan. 6, 2005 in the name of inventors K. S. Grant et al. and entitled “Traffic Management Using In-band Flow Control and Multiple-rate Traffic Shaping,” commonly assigned herewith and incorporated by reference herein, discloses improved techniques for communicating information between a link layer device and a physical layer device, so as to facilitate backpressure detection and related traffic management functions, particularly in high channel count applications supporting a large number of ingress and egress links.
U.S. Patent Application Publication No. 2005/0138259, published Jun. 23, 2005 in the name of inventors A. Q. Khan et al. and entitled “Link Layer Device with Configurable Address Pin Allocation,” commonly assigned herewith and incorporated by reference herein, provides an improved approach to allocating address bits to sub-buses of an interface bus between a physical layer device and a link layer device.
U.S. Patent Application Publication No. 2005/0169298, published Aug. 4, 2005 in the name of inventors A. Q. Khan et al. and entitled “Link Layer Device With Non-Linear Polling of Multiple Physical Layer Device Ports,” commonly assigned herewith and incorporated by reference herein, provides improved polling techniques that overcome polling delay problems associated with fixed linear polling of a large number of MPHYs, while also avoiding the need for increased buffer sizes or additional interface pins. Generally, an efficient and flexible non-linear polling approach is provided which, in an illustrative embodiment, allows the polling sequence to be altered dynamically based on particular data transfers that are occurring between a link layer device and one or more physical layer devices in a communication system.
Despite the considerable advantages provided by techniques in the above-noted applications, further link layer device improvements are needed, particularly in terms of clock processing in a link layer processor or other link layer device.
For example, link layer processors developed for high channel count applications are typically designed to support a large number of ingress and egress links, each of which requires a phase-locked loop (PLL) clock recovery circuit. Thus, a separate instantiation of a PLL block with associated control and configuration registers would generally be required for each ingress and egress link. In addition, for a link layer processor in which Synchronous Residual Time Stamp (SRTS) processing capability is to be provided, each ingress and egress link typically has its own separate set of SRTS logic. Also, implementations using a buffer adaptive approach often require a very wide phase accumulator in order to accommodate the large cell delay variations associated with certain types of ATM traffic, such as ATM Adaptation Layer 1 (AAL-1) traffic. These and other issues lead to significant disadvantages in terms of excessive area and power requirements for the link layer processor. Moreover, the large phase transients caused by AAL-1 cell delay variations can lead to high PLL clock acquisition time and increased phase jitter.
Accordingly, what is needed is an area and power efficient architecture for implementing digital PLLs in high channel count link layer processors, in a manner that provides flexibility for accommodating various clock rates and clock transport mechanisms associated with ATM traffic, or other types of traffic such as time division multiplexed (TDM) traffic. Techniques are also needed for reducing PLL clock acquisition time and phase jitter.